2D and 3D Interconnect Fabrication by Picosecond Laser Induced Forward Transfer

Introduction Interconnects are an important cost driver in advanced 3D chip packaging. This holds for Through Silicon Vias (TSV) for chip stacking, but also for other integrated Sitechnology. Especially in applications with a low number (<100 mm) of relatively large (10-20 μm diameter), high aspect ratio (1:5-1:20) interconnects, conventional wafer level plating processes are slow and become cumbersome with increasing aspect ratio, thus becoming cost ineffective. Hence, industrially feasible alternative deposition processes are of interest for advanced interconnects.